KRON4 News

Post Singulation Die Alignment at Wafer Probe

Complete Probe Solutions developed Single Die Alignment for automatically probing die that are not precisely positioned or misaligned relative to each other. The Single Die Alignment feature makes it ...
Semiconductor Engineering

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding

A technical paper titled “Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding” was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. “A collective ...
Design-Reuse

CEA-Leti & Intel Report Die-to-Wafer Self-Assembly Breakthrough Targeting High Alignment Accuracy and Throughput

SAN DIEGO – June 2, 2022 – In a breakthrough for the future of die-to-wafer (D2W) bonding, CEA-Leti and Intel have optimized a hybrid direct-bonding, self-assembly process that has the potential to ...
Semiconductor Engineering

Intra-Field Stress Impact on Global Wafer Deformation

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., ...
New Electronics

Die-to-wafer self-assembly breakthrough delivers accuracy and throughput

In what is being described as a breakthrough for the future of die-to-wafer (D2W) bonding, CEA-Leti and Intel have optimised a hybrid direct-bonding, self-assembly process that has the potential to ...
Electronics Weekly

Imec develops die-to-wafer bond process with 2µm pad pitch

Imec has developed a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <350nm die-to-wafer overlay error, achieving good electrical yield. Such ...
Physics World

Wafer mask alignment: Queensgate focuses on the move to 300 mm

Modern semiconductor fabrication involves aligning silicon wafers and photolithography masks to nanometre precision. As the industry shifts from using 200 mm diameter wafers to 300 mm wafers, ...
AZOM

Automating Semiconductor Inspection for High Performance Quality Control

Semiconductor circuits (patterns) printed on semiconductor wafers (substrates) are shrinking, while such substrates are becoming larger in physical size. Over the years, the inspection of patterned ...
EDN

Cascade debuts software to align wafers in probers

BEAVERTON, Ore.–Probe-card specialist Cascade Microtech Inc. rolled out a software line to align wafers and RF calibration substrates in wafer probe applications. The company's Nucleus Vision 3.0 ...
EDN

Post-test inspection boosts die yields

Wafers produced for products as diverse as LEDs and MP3 players vary greatly in function, but they have one thing in common: They often undergo optical inspection after they pass an electrical test.
Nasdaq

Applied Materials Unveils eBeam Metrology System that Enables a New Playbook for Patterning Advanced Logic and Memory Chips

Today’s leading-edge chip designs require a new class of metrology that goes beyond optical target-based approximation, statistical sampling and single-layer control PROVision® 3E system combines ...